View SMB118_3492161.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SMB118/218 ? summit microelectronics, inc. 2008 757 n. mary avenue ? sunnyvale ca 94085 ? phone 408 523-1000 ? fax 408 523-1266 1 http://www.summitmicro.com/ 2107 3.0 10/15/2008 six-channel programmable dc-dc power managers with battery charger introduction ? digital programming of all major parameters via i 2 c interface and non-volatile memory o output voltage setpoint/margining o sequencing & digital soft start o enable/disable outputs independently o input/output uv/ov voltage thresholds o pwm/pfm mode ? six programmable regulator channels with 1.5% accuracy o three synchronous step-down (buck) with internal pfets o one configurable step-up (boost) or synchronous step-down (buck) o one step-up (boost) o one adjustable output voltage ldo ? programmable linear li-ion battery charger o precharge/fast charge/termination current o fast charge voltage threshold o float voltage ? +2.7v to +6.0v input range (higher system voltages supported) ? built-in current limiting, uv/ov, and thermal protection ? highly accurate reference and output voltage ? 1mhz pwm frequency and power-saving automatic pfm mode ? 96 bytes of user configurable nonvolatile memory applications ? portable media players ? digital camcorders/still cameras ? smart pda/camera phones ? handheld gps/pda?s ? tft-lcd displays/monitors/tvs the SMB118 and smb218 are highly integrated and flexible six- channel power managers designed for use in a wide range of portable applications. the built-in digital programmability allows system designers to custom tailor the device to suit almost any multi-channel power supply application from digi tal camcorders to mobile phones. the SMB118 and smb218 integrate all the essential blocks required to implement a complete seven-channel power subsystem including three synchronous step-down ?buck? conv erters, one configurable step-up ?boost? or step-down synchronous ?buck? converter, one step-up ?boost? converter, one linear regula tor (ldo) and a fully programmable li-ion battery charger. additionally sophisticated power control/monitoring functi ons required by complex systems are built-in. these include digitally programmable output voltage setpoint, power- up/down sequencing, enable/disable, margining and uv/ov input/output monitoring on all channels. the integration of features and built-in flexibility of the SMB118 and smb218 allows the system designer to create a ?platform solution? that can be easily modified via software without major hardware changes. combined with the re-programmability of the SMB118 and smb218, this facilitates rapid design cycles and proliferation from a base design to futures generations of product. the SMB118 and smb218 are suited to battery-powered applications with an input range of +2.7v to +6.0v and provide a very accurate voltage regulation. communication is accomplished via the industry standard i 2 c bus. all user-programmed settings are stored in non- volatile eeprom of which 96 bytes may be used for general-purpose memory applications. the commercial operating temperature range is 0c to +70c, the industrial operating range is ?40c to +85c, and the available package is a 48-pad 7mm x 7mm qfn. SMB118/218 +0.5v to vin (prog.) li-ion battery or +2.7v to +6.0v analog/rf i2c/smbus 3 step- down (buck) channels step-up (boost) channel system control and monitoring healthy output shutdown +0.5v to +35v (prog.) memory, i/o +0.5v to vin (prog.) cpu core +0.5v to vin (prog.) dsp/codec step-up (boost) or step-down (buck) channel li-ion charger +4.5v to +6.0v dc in pushbutton power +0.5v to +35v (prog.) led backlight drive ldo channel +1.5v to +3.75v (prog.) mcu/rtc reset output figure 1 ? applications block diagram featuring the SMB118/218 six-channel, programmable dc/dc converters. these integrated power supply and battery managers provide precision regulation, monitoring, cascade sequencing, output margining and battery charging. simplified applications drawing features & applications please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 2 the SMB118 and smb218 are fully programmable power supply and battery managers that regulate, sequence, monitor, and margin, an entire power subsystem while controlling the charging of a lithium-ion battery pack. they feature 6 voltage outputs, consisting of: three synchronous pwm ?buck? step-down converters, one configurable pwm ?boost or buck? converter, one pwm ?boost? step-up converter, one low dropout (ldo) linear regulator, and a fully programmable li-ion battery charger. the SMB118 and smb218 regulate each of the six output channels to an accuracy of 1.5% (typical). the output is individually programmed and can be reprogrammed via the i 2 c interface. in addition, several sophisticated power management functions are built-in. the SMB118 and smb218 are capable of power-on/off cascade sequencing where each channel can be assigned one of six sequenc e positions. supplies may also be individually powered on/off through an i 2 c command or by assertion of the enable pin. cascade sequencing, unlike time based sequencing, uses feedback to ensure that each output is valid before the next channel is enabled. each output voltage and the battery are monitored for under-voltage and over-voltage conditions, using a comparator based scheme. in the event of a fault, all supplies may be sequenced down or immediately disabled. multiple output stat us pins are provided to notify host processors or other supervisory circuits of system faults. the SMB118 and smb218 feature an under-voltage lockout (uvlo) circuit to en sure the ic will not power up until the battery voltage has reached a safe operating voltage. the uvlo function exhibits hysteresis, ensuring that noise on the supply rail does not inadvertently cause faults on the internally regulated supply. in the event of a system fault, all monitored supplies may trigger fault actions such as power-off, or force-shutdown operations. each output on the SMB118 and smb218 may also be turned off individually at any point through an i 2 c command or by a programmable enable pin. when used in portable applications, the devices are powered from the main system battery. this input is continuously monitored for under-voltage conditions. there are two under-voltage settings for this supply; both are user programmable and have a corresponding status pin. when the first threshold level is reached, the power_fail pin is asserted and latched. when the second threshold level is reached on the main supply, the nbatt_fault pin is asserted. the SMB118 and smb218 are equipped with three synchronous buck outputs and one ?buck-or-boost? output that use a 1mhz oscillator frequency. the feedback circuitry on each step-down channel is simplified by an internal programmable resistor divider (buck-or-boost uses exte rnal resistor divider). the SMB118 and smb218 are equipped with one boost output that uses a 1mhz osc illator, and an asynchronous topology reducing the necessity for an additional external mosfet driver. this boost output also uses an external p-channel sequencing mosfet to isolate load from the battery when not needed. a low dropout (ldo) linear regulator with an adjustable 1.5v to 3.75v output provides a small dropout voltage and ripple free supply that is optimal for ?always on? microcontrollers. the ldo has a separate input supply pin. the SMB118 and smb218 provide margining control over all of its output voltages. through an i 2 c command, all outputs can be margined by up to 10% of the nominal output voltage. 7-level dynamic voltage management is also available for one of the channels. in addition, each output is slew rate limited by soft-start circuitry that is user programmable and requires no external capacitors. all programmable settings on the SMB118 and smb218 are stored in non-volatile registers and are easily accessed and modified over an industry standard i 2 c serial bus. for fastest possible production times summit offers an evaluation card and a graphical user interface (gui). general description please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 3 SMB118 package and pin description SMB118 48-pad qfn top view shdn sda sw4 ldoout2 vin4 bcsl fb4 scl comp4 ldoin2 drvl4 bcsh 1 SMB118 7mm x 7mm qfn-48 (thermal pad = gnd) 2 3 20 4 17 19 18 5 6 7 38 21 37 36 39 41 42 40 8 9 10 11 12 13 14 34 35 33 27 24 26 25 22 23 28 15 16 31 32 29 30 45 44 43 46 47 48 comp6 dcin fb6 bstat dock_dc compb3 pchseq3 fb5 comp5 vbatt drvl6 drvl5 vin6 vin5 csl1 fb1 csh1 pchseq1 comp1 nbatfault drvl3 vin3 drvh3 compa3 vddcap nalert pwrfail drvl1 pwr_en sw6 bfetdrv bsense tsense healthy sw5 nreset please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 4 smb218 48-pad qfn top view shdn sda sw4 ldoout2 vin4 bcsl fb4 scl comp4 ldoin2 drvl4 bcsh 1 smb218 7mm x 7mm qfn-48 (thermal pad = gnd) 2 3 20 4 17 19 18 5 6 7 38 21 37 36 39 41 42 40 8 9 10 11 12 13 14 34 35 33 27 24 26 25 22 23 28 15 16 31 32 29 30 45 44 43 46 47 48 comp6 dcin fb6 bstat dock_dc compb3 pchseq3 fb5 comp5 vbatt drvl6 drvl5 vin6 vin5 csl1 fb1 csh1 pchseq1 comp1 nreset drvl3 vin3 drvh3 compa3 vddp nalert pwrfail drvl1 pwr_en sw6 bfetdrv bsense tsense healthy sw5 vddcap smb218 package and pin description please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 5 figure 2a ? typical application schematic of the smb1 18 (qfn-48) showing external circuitry necessary to configure the output channels as: step-up, ldo, step-down outputs and battery charger. SMB118 typical application SMB118 comp6 sw6 fb6 comp5 sw5 fb5 gnd vbatt nreset sda scl +0.5v to vin7(+2.5v typ) @ 500ma +2.7 to +6.0v vddcap pwr_en compa3 +0.5v to +35v (+5v typ) @ 600ma buck or boost pchseq3 drvl3 drvh3 bfetdrv bsense bcsh tsense rcsb +3.0v to +4.2v 1-cell li-ion battery pack 10k ? ntc dock_dc vin6 vin5 comp4 fb4 sw4 vin4 compb3 nalert bstat drvl6 drvl5 +0.5vto vin7(+2.5v typ) @ 500ma +0.5v to vin7(+2.5v typ) @ 500ma drvl4 vbatt to +35v (+15v typ) @ 200ma comp1 drvl1 fb1 rsense2 csh1 csl1 shdn pchseq1 bcsl vin3 vusb usb/ac charging vdc = +6v ldoout2 ldoin2 +1.5v to 3.75 @ 65ma healthy nbatt_fault power_fail dcin please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 6 figure 2a ? typical application schematic of the smb2 18 (qfn-48) showing external circuitry necessary to configure the output channels as: step-up, ldo, step-down outputs and battery charger. smb218 typical application smb218 comp6 sw6 fb6 comp5 sw5 fb5 gnd vbatt nreset sda scl +0.5v to vin7(+2.5v typ) @ 500ma +2.7 to +6.0v vddcap pwr_en compa3 +0.5v to +35v (+5v typ) @ 600ma buck or boost pchseq3 drvl3 drvh3 bfetdrv bsense bcsh tsense rcsb +3.0v to +4.2v 1-cell li-ion battery pack 10k ? ntc dock_dc vin6 vin5 comp4 fb4 sw4 vin4 compb3 nalert bstat drvl6 drvl5 +0.5vto vin7(+2.5v typ) @ 500ma +0.5v to vin7(+2.5v typ) @ 500ma drvl4 vbatt to +35v (+15v typ) @ 200ma comp1 drvl1 fb1 rsense2 csh1 csl1 shdn pchseq1 bcsl vin3 vusb usb/ac charging vdc = +6v ldoout2 ldoin2 +1.5v to 3.75 @ 65ma healthy power_fail dcin vddp please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 7 pin descriptions pin # pin name pin type pin description 1 nalert output fault interrupt ? latched, open-drain active low output. flag for all fault conditions (multiplexed) 2 pwr_en input enable input. pwr_en is programmable to activate one or more channels. this pin can be programmed to latch and act as a debounced, manual push button input. active high when level triggered, active low when used as a push- button input. a software power-off command overrides this pin. 3 drvl3 output buck or boost converter low-side drive ? connect to nfet gate 4 drvh3 output buck converter high-side driv e ? connect to pfet gate (for buck only) 5 vin3 power channel 3 controller power ? connect to +2.7v to +6.0v to supply internal fet drivers 6 compa3 input buck or boost primary compensation ? connect to r/c compensation network 7 pchseq3 output boost converter 3 sequence ? connect to pfet gate for boost channel on/off and sequencing. must be tied to ground when unused. 8 compb3 input buck or boost secondary compensation ? connect to r/c compensation network 9 healthy output output monitor ? open drain active-high output asserts when all output channels are within uv/ov limits (ignoring disabled outputs) 10 power_fail output battery/input monitor. detects low input voltage. latched open-drain active high output. associated threshold must be set higher than nbatt_fault threshold. 11 comp5 input buck converter 5 compensation pi n ? connect to r/c compensation network 12 fb5 input buck converter 5 feedback pin ? connect directly to output 13 sw5 input/o utput buck converter 5 switch pin ? connect to drains of nfet 14 vin5 power buck converter 5 power ? connect to +2.7v to +6.0v to supply internal pfet 15 drvl5 output buck converter 5 low- side drive ? connect to nfet gate 16 drvl6 output buck converter 6 low- side drive ? connect to nfet gate 17 vin6 power buck converter 6 power ? connect to +2.7v to +6.0v to supply internal pfet 18 sw6 input/ output buck converter 6 switch pin ? connect to drains of nfet 19 fb6 input buck converter 6 feedback pin ? connect directly to output 20 comp6 input buck converter 6 compensation pi n ? connect to r/c compensation network 21 dcin output dc input valid ? active high open drain indicates presence of dc input voltage (docking) with programmable threshold 22 bstat output battery charger status output ? open dr ain output asserts low when battery is charging and releases when charging is terminated/interrupted. can be configured to blink while charging. when configured to blink, it will blink once every second while pre-charging and twice per second while fast and taper charging. 23 dock_dc power docking connector detector. dock_dc detects presence of external dc input and asserts dcin pin. provides power to the chip when greater than vbatt. voltage on this pin must be greater th an dock_dc trip point (programmable) for battery charging to be initiated. when voltage is present on dock_dc pin the shdn pin is bypassed. SMB118: nbatt_fault output SMB118: battery/input monitor. nbatt_fa ult detects low input voltage. open- drain active low output. associated threshold must be set lower than power_fail threshold. 24 smb218: nreset output smb218: reset output. releases with programmable delay after all selected outputs are valid (see uv/ov trip points). open-drain active low output. please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 8 pin descriptions (cont.) pin number pin name pin type pin description SMB118: nreset output SMB118: reset output. releases with programmable delay after all selected outputs are valid (see uv/ov trip points). open-drain active low output. 25 smb218: vdd_cap power smb218: vdd bypass ? c onnect to vdd bypass capacitor with 10uf capacitor. SMB118: vdd_cap power SMB118: vdd bypass ? c onnect to vdd bypass capacitor with 10uf capacitor. 26 smb218: vddp power smb218: power input for the boost converter. connect to +2.7v to +6.0v voltage source. must be at same volt age as source of pfet for the boost converter. 27 vbatt power power input for controller. connect to +2.7v to +6.0v voltage source bypass with a 0.1uf ceramic capacitor close to the pin 28 drvl1 output boost converter 1 lo w-side drive ? connect to nfet gate 29 fb1 input boost converter 1 feedback pin ? connect to external resistor divider 30 csh1 input boost converter 1 current sense high ? co nnect to high side of sense resistor. this input is used to kelvin sense the voltage across the current sense resistor. 31 csl1 input boost converter 1 current sense low ? c onnect to low side of sense resistor. this input is used to kelvin sense the voltage across the current sense resistor. 32 comp1 input boost converter 1 compensation pin ? connect to r/c compensation network 33 pchseq1 output p-channel mosfet sequencing pin. connect to pfet gate for boost channel on/off and sequencing. internally connected to a 100ua current sink to pull pfet gate resistor from vdd to gnd to enable sequencing. tie to gnd when unused. 34 bfetdrv output battery charger fet drive ? connects to gate of a pfet to control battery charging current 35 bsense input battery voltage sens e ? connect directly to pos itive terminal of battery 36 tsense input battery temperature sense ? connect to ?t emp? terminal of battery pack. this pin injects a programmable current into the ntc thermistor internal to the battery pack and measures the resulting current to detect temperatures. place a 24.9k resistor, for 10k ntc, from this node to ground. 37 bcsh input charge current sense ? connect to high-s ide of charge current sense resistor. this input is used to kelvin sense the voltage across the current sense resistor. 38 ldoin2 power ldo power input ? connect to +2.7v to +6.0v to supply internal ldo 39 ldoout2 input/ output ldo output/feedback 40 sw4 input/ output buck converter 4 switch pin ? connect to drains of nfet 41 vin4 power buck converter 4 power ? connect to +2.7v to +6.0v to supply internal pfet 42 drvl4 output buck converter 4 low- side drive ? connect to nfet gate 43 bcsl input charge current sense resistor. connect to low side of charge current sense resistor. do not attach to battery node at any other point. 44 fb4 input buck converter 4 feedback pin ? connect directly to output 45 comp4 input buck converter 4 compensation pi n ? connect to r/c compensation network 46 shdn input shutdown ? when high this input disables all functions of the SMB118 for low power operation. when voltage is pres ent on the dock_dc input the part will exit the shutdown state, regardless of the state of the shutdown input. 47 sda input/ output i 2 c data 48 scl input i 2 c clock pad (49) drvgnd ground power ground ? internally connect to under package pad. connect to isolated pcb ground plane/flood please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 9 recommended operating conditions absolute maximum ratings temperature under bias??????.-55 c to 125 c storage temper ature............................ -65 c to 150 c terminal voltage with respect to gnd: vbatt............................................. -0.3v to +6.5v vin[7:5], ldoin3............................ -0.3v to +6.5v all others ........................................ -0.3v to +6.5v output short circ uit current ............................... 100ma lead solder temper ature ( 10 s).......................... 300 c junction temperature........ ...............?? .....?...150c esd rating per jedec???????....??..2000v latch-up testing per jedec???..?....?? 100ma commercial temperature range ................0c to +70c industrial temperature range ................ -40c to +85c vbatt.......................................................+2.7v to +6.0v vin[6:3], ldoin2 ......................................+2.7v to +6.0v dock_dc.................................................+4.5v to +6.0v 48-lead 7x7 qfn package thermal resistance ( ja ) die paddle not attac hed to pcb .......................... 53 c/w die paddle attached to pcb............................. 22.9c/w moisture classification level 3 (msl 3) per j-std- 020 reliability characteristics data retentio n ................................................. 100 years endurance ................................................ 100,000 cycles dc operating characteristics (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit general v batt input supply voltage +2.7 +6.0 v vin[6:3], ldoin2 regulator power supply voltage +2.7 +6.0 v v batt rising 2.3 2.4 v v uvlo under-voltage lockout voltage v batt falling 2.1 v i dd-active active supply current all regulators and monitors enabled ? no load, v batt = 4.2v 3.3 4.5 ma i dd-standby standby supply current all regulators disabled, monitors active, v batt = 4.2v 135 300 a i dd-shutdown shutdown supply current all regulators and monitors disabled 0.6 5 a t shdn thermal shutdown temp 160 o c t hyst thermal shutdown temp hysteresis 20 o c vdd_cap voltage on vdd_cap pin all logic derived from this voltage, no load 2.4 2.5 2.6 v t = 0c to +70c 900 1000 1100 f osc oscillator frequency (note 1) t = -40c to +85c 850 1000 1150 khz note - the device is not guaranteed to function outside its operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions out side those listed in the operational sectio ns of the specification is not implied. exposure to any absolute maximum rating for extended period s may affect device performance and reliability. devices are esd sensitive. handlin g p recautions are recommended. please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 10 dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) channel 1 ? step-up boost v out voltage (nominal set point) v batt = 4.2v, i load = 0a vin +35 v v fb feedback voltage reference programmable in 4mv steps 0 1 v ? v fb feedback voltage accuracy at fb[2:1] pin (note 2) v fb =0.836v -3 1 +3 % g m error amp transconductance 145 umho i ea error amp output drive 20 a 0.8 r cs cs amplifier transresistance r sense = 0.1 ?, r load =350ma 1.6 ? i ol-seq pchseq pull down current v ol-seq = 1v 60 100 a output high 6.0 ? r drvl ls gate drive impedance output low 2.5 ? v cl clamp threshold voltage programmable 1.0, 1.1, 1.2, 1.5v 1.0 1.5 v v cl_acc clamp threshold voltage accuracy clamp threshold 1.0 and 1.5v 5 % maximum (clamp on) 85 90 98 % d.c. duty cycle minimum, pwm mode 16 30 % channel 2 ? ldo v out voltage (nominal set point) ldoin2=4.2v, i load =0a +1.5 +3.75 v ? v out voltage accuracy ldoin3=4.2v, i load =0a, v out =2.5v -2.5 0.5 +2.5 % ? v line line regulation ldoin2=4.2v, i load =0a 1 mv/v ? v load load regulation vo=2.5, vin = 4.2v 1 mv/ ma ? v trans load transient regulation step load: 5ma to 50ma c out = 10uf 50 mv psrr input ripple rejection ldoin2=3.8v, v out =3.3v i load =50ma, v p-p =200mv, f=1khz 45 db i outmax maximum output current ldoin2=3.2v, v out = 2.5v 50 75 ma v do dropout voltage i load =50ma 150 mv please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 11 dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) channel [6:4] ? step-down buck v out voltage (nominal set point) vin [6:4] 4.2v, i load =0a +0.5 vin v note 2, v out = 2.5v, t = -40c to +85c -2 1 +2 % ? v out voltage accuracy note 2, v out = 1.2v, t = 0c to +70c -2 1 +2 % v fb feedback voltage reference range programmable in 4mv steps 0 1 v g m error amp transconductance 160 umho i ea error amp output drive 20 a r cs cs amplifier transresistance i load = 500ma 1.2 ? r hs hs switch resistance i load = 500ma 320 m ? output high 5.5 ? r drvl ls gate drive impedance output low 2.7 ? v cl clamp threshold voltage programmable 1.0, 1.1, 1.2, 1.5v 1.0 1.5 v v cl_acc clamp threshold voltage accuracy clamp threshold 1.0 and 1.5v 5 % maximum, v batt = 4.2v 100 % d.c. duty cycle minimum, pwm mode, v batt = 4.2v 15 30 % please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 12 dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) channel 3 ? step-down buck or step-up boost v out voltage (nominal set point, buck) v batt =4.2v, i load =0a +0.5 +vin v v out voltage (nominal set point, boost) v batt =4.2v, i load =0a +vin +35 v v fb feedback voltage reference range programmable in 4mv steps 0 1 v ? v fb feedback voltage reference fb3 pin, v fb = 0.656v, note 2 -2 +2 % a vol error amp open loop gain 60 db i ea error amp output drive 20 a i eab error amp input bias current 9 10 na output high 15 ? r drvh hs gate drive impedance (buck only) output low 15 ? output high 15 ? r drvl ls gate drive impedance output low 15 ? maximum, v batt = 4.2v 80 90 98 % d.c. (boost) duty cycle minimum, pwm mode, v batt = 4.2v 6 10 % maximum, v batt = 4.2v 100 % d.c. (buck) duty cycle minimum, pwm mode, v batt = 4.2v 7 11 % please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 13 dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit battery charger (note 3), dock_dc=5v v dockdc input voltage vbatt=3.6v 5.0 v v prechg precharge voltage threshold range programmable: 100mv steps 2.500 3.200 v v prechg_acc precharge voltage threshold accuracy vbatt rising, v prechg = 2.5v and 3.2v 20 mv i prechg nominal precharge current range r csb =0.1 ? , 15ma steps 25 250 ma ? i prechg precharge current tolerance i prechg = 100ma 70 100 130 ma i chg nominal fast charge current r csb =0.1 ? , 60ma steps 100 1000 ma ? i chg fast charge current tolerance i chg = 520ma 485 520 565 ma v flt float voltage range 20mv steps 4.000 4.620 v ? v flt float voltage tolerance v flt = 4.2v -1.2 0.5 +1.2 % v flt_hyst float voltage hysteresis (recharge threshold) vbatt falling, v flt - v flt_hyst 100 mv i term charge termination current range r csb =0.1 ? , 15ma steps 100 145 ma ? i term termination current tolerance i term = 100ma 50 100 170 ma t hi charge cutoff temp (high) 5 o c steps +30 +65 o c t lo charge cutoff temp (low) 5 o c steps -20 +15 o c t tsense therm bias current 80 100 130 a t precharge precharge timer duration adjustable (3 setpoints) 2621 s t charge charge timer duration adjustable (3 setpoints) 20972 s v pddcth programmable dock_dc threshold range programmable in 200 mv increments 3.4 4.8 v v pddcthacc dock_dc threshold accuracy v pddcth = 4.6v -4 +4 % please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 14 note 1: contact summit factory for other frequency settings. note 2: voltage, current and frequency accuracies are only guaranteed for factory-programmed settings. changing any of these pa rameters from the values reflected in the customer s pecific csir code will result in ina ccuracies exceeding t hose specified above. note 3: the SMB118 and smb218 devices are not intended to functi on as a battery pack protector. battery packs used in conjuncti on with these devices need to provide adequate internal protection and to comply with the corresponding battery pack specifications. note 4: guaranteed by design and characterization ? not 100% tested in production. dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit v ih input high voltage 0.7 x vdd_cap v v il input low voltage 0.3 x vdd_cap v v pbfth programmable nbatt_fault threshold range programmable in 150 mv increments 2.55 3.60 v ? v pbfth nbatt_fault accuracy v pbfth =3.15v -3 +4 % v ppfth programmable power_fail threshold range programmable in 150 mv increments 2.55 3.60 v ? v ppfth power_fail accuracy v ppfth =3.3v -3 +4 % -5 -10 -15 p uvth programmable under voltage threshold relative to nominal operating voltage. ch1 to ch7. note 3. -15 -20 -25 % 5 10 15 p ovth programmable over voltage threshold relative to nominal operating voltage. ch1 to ch7. note 4. 15 20 25 % please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 15 ac operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit 1.5 12.5 25 t ppto programmable power-on sequence timeout period. programmable power-on sequence position to sequence position delay. 50 ms 1.5 12.5 25 t dpoff programmable power-off sequence timeout period. programmable power-off sequence position to sequence position delay. 50 ms 25 50 100 t prto programmable reset time-out delay programmable time following assertion of last supply before nreset pin is released high. 200 ms off 50 100 t pst programmable sequence termination period time between active enable in which corresponding outputs must exceed there programmed under voltage threshold. if exceeded, a force shutdown will be initiated. 200 ms 0 25 100 t pdb pwr_en de-bounce period when pwr_en is programmed as power on pin. 400 ms t pfto power_fail timeout period timeout begins after latch is cleared. 3 ms t bfto nbatt_fault timeout period timeout begins after fault conditions cleared. 3 ms t pgf programmable glitch filter period for which fault must persist before fault triggered actions are taken. present on all buck, boost, and inverting supplies. 3 s please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 16 ac operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit 400 200 100 66.7 50 33.3 25 sr ref programmable slew rate reference adjustable slew rate factor proportional to output slew rate. 20 v/s please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 17 note 5: guaranteed by design figure 3 ? i 2 c timing diagram i 2 c-2 wire serial interface ac ope rating characteristics ?100 khz (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) 100khz symbol description conditions min typ max units f scl scl clock frequency 0 100 khz t low clock low period 4.7 s t high clock high period 4.0 s t buf bus free time before new transmission - note 5 4.7 s t su:sta start condition setup time 4.7 s t hd:sta start condition hold time 4.0 s t su:sto stop condition setup time 4.7 s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 s t dh data output hold time scl low (cycle n+1) to sda change 0.2 s t r scl and sda rise time note 5 1000 ns t f scl and sda fall time note 5 300 ns t su:dat data in setup time 250 ns t hd:dat data in hold time 0 ns ti noise filter scl and sda noise suppression 100 ns t wr_config write cycle time config configuration registers 10 ms t wr_ee write cycle time ee memory array 5 ms timing diagrams t r t f t high t low t su:sta t hd:sta t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t wr (for write operation only) i 2 c timing diagrams please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 18 applications information device operation power supply the SMB118 and smb218 can be powered from an input voltage between +2.7 and +6 volts applied between the vbatt pin and ground. the input voltage applied to the vbatt pin is filt ered by an external filter capacitor attached between the vdd_cap pin and ground; this filtered voltage is then used as an internal vdd supply. the vdd_cap node is monitored by an under-voltage lockout (uvlo) circuit, which prevents the outputs from turning on when the voltage at this node is less than the uvlo threshold. when the voltage on the dock_dc input exceeds that on the vbatt input the vbatt pin goes into a high impedance state and no longer powers the devices, and the dock_dc pin becomes the new power input. shutdown the SMB118 and smb218 are equipped with a shutdown pin that disconnec ts power from the devices and reduces the current consumption to 0.6 a when asserted. when the shdn pin is pulled high, all outputs will be disabled and the SMB118 and smb218 will not respond to i 2 c commands. to exit the shutdown mode the shdn pin can be pulled high, or voltage can be applied to the dock_dc input. when voltage is present on the dock_dc input the device will exit the shut down mode and operate normally. power-on/off control sequencing can be initiated: automatically, by a volatile i 2 c power on command, or by asserting the pwren pin. when the pwren pin is programmed to initiate sequencing, it can be level or edge triggered. the pwren input has a programmable de-bounce time of 100, 50, or 25ms. the de-bounce time can also be disabled. when configured as a push-button enable, the pwren must be low longer than the debounce time before sequencing can commence, and pulled low for the same period to disable the channels. when a software power off command is written to the volatile memory the system will be powered off regardless of the state of the pwren pin. enable each output can be enabled and disable by an enable signal. the enable signal is can be provided from either the pwren pin or by the contents of the enable register. when enabling a channel from the enable register, the register contents default stat e must be set so that the output will be enabled or disabled following a por (power on reset). the default state is programmable. cascade sequencing each channel on the SMB118 and smb218 may be placed in any one of 6 unique sequence positions, as assigned by the configurabl e non-volatile register contents. the SMB118 and smb218 navigate between each sequence position using a feedback-based cascade-sequencing circuit. cascade sequencing is the process in which each channel is continually compared against a programmable reference voltage until the voltage on the monitored channel exceeds the reference voltage, at which point an internal sequence position counter is incremented and the next sequence position is entered. in the event that a channels enable input is not asserted when the channel is to be sequenced on, that sequence position will be skipped and the channel in the next sequence position will be enabled. figure 4 ? power on sequencing waveforms. time = 4ms/devision, scale = 1v/devision ch 1 = 3.3v output (yellow trace) ch 2 = 2.5v output (blue trace) ch 3 = 1.8v output (purple trace) ch 4 = 1.2v output (green trace) power on/off delay there is a programmable delay between when channels in subsequent sequence positions are enabled. the delay is programmable at 50, 25, 12.5 and 1.5ms intervals. this delay is programmable for each of the four sequence positions. manual mode the SMB118 and smb218 provide a manual power-on mode in which each channel may be enabled please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 19 individually irrespective of the state of other channels. in this mode, the enable signal has complete control over the channel, and all sequencing is ignored. in manual mode, channels will not be disabled in the event of a uv/ov fault on any output or the vbatt pin. force-shutdown when a battery fault occurs, a uv/ov is detected on any output, or an i 2 c force-shutdown command is issued, all channels will be immediately disabled, ignoring sequence positions or power off delay times. sequence termination timer at the beginning of each s equence position, an internal programmable timer will begin to time out. when this timer has expired, the SMB118 and smb218 will automatically perform a force-shutdown operation. this timer is user programmable with a programmable sequence termination period (t pst ) of 50, 100, 200 ms; this function can also be disabled. power off sequencing the SMB118 and smb218 have a power-off sequencing operation. during a power off operation, the supplies will be powered off in the reverse order they where powered on in. during the power off sequencing, all enables are ignored. when a power-off command is issued the devices will set the sequence position counter to the last sequence position and disable that channel without soft-start control; once off, the power off delay for the channel(s) in the next to last sequenc e position will begin to timeout, after which that channel(s) will be disabled. this process will continue until all channels have been disabled and are off. the programmable if a channel fails to turn off within the sequence termination period, the sequence termination timer will initiate a force shutdown, if enabled. input and output voltage monitoring the SMB118 and smb218 monitor all outputs for under-voltage (uv) and over-voltage (ov) faults. the monitored levels are user programmable, and may be set at 5, 10, 15, and 20 percent of the nominal output voltage. the vbatt pin is monitored for two user programmable uv settings. the vbatt uv settings are programmable from 2.55v to 3.45v in 150mv increments. once the uv/ov voltage set points have been violated, the SMB118 and smb218 can be programmed to sequence off the supplies (power off), turn off all supplies simultaneously (for ce shutdown), assert the nreset/healthy pin, or take no action. soft start the SMB118 and smb218 provide a programmable soft-start function for all pwm outputs. the soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. the soft start slew rate is proportional to the product of the output voltage and a slew rate reference. this global reference is programmable and may be set to 400, 200, 100, 67, 50, 33, 25, and 20 volts per second. the slew rate control can also be disabled on any channel not requiring the feature. dynamic voltage management the SMB118 and smb218 have two additional voltage set points, dynamic voltage control high and low settings. together with the nominal voltage setting, three pre-determined voltage levels can be used. the three voltage levels are ideal for situations where a core voltage needs to be reduced for power conservation. the dynamic voltage control high and low settings have the same voltage range as the controllers? nominal output voltage. these settings are stored in the non- volatile configuration registers and can be set by a write to volatile configuration regi sters. the dynamic voltage control command registers contain two bits for each channel that adjust the output voltages to the high, low or nominal set point after a volatile i2c write command. a seven level dynamic voltage control option is available for channel 3. when enabled, seven level dynamic voltage control allows channel 3 to be dynamically modified to one of seven pre-determined voltage levels. this transition is made by means of a volatile i 2 c write command. when all channels are at their voltage setting, a bit is set in the dynamic voltage control status registers. note: configuration writes or reads of registers should not be performed while dynamic voltage management. + ? vref r1 r2 comp1 vout vout= vref* (1 + r2/r1) soft-start slew rate=srref* (1 + r2/r1) figure 5 ? the output voltage is set by the voltage divider . the vref voltage is programmable from 0 to 1.0 volt in 4mv increments via the i 2 c interface applications information (continued) please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 20 figure 6 ? power-on sequencing flow chart. applications information (continued) restart after power-off or force-shutdown i2c power on command begin sequencing sequence position 1 current sequence position power on delay next sequence position channel enabled soft-start wait for enable monitor soft-start pwren pin asserted channel not enabled vout=>uv enable low enable high vout<=uv please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 21 applications information (continued) battery monitoring the battery voltage is monitored for two user- programmable uv settings via the vbatt pin. in addition, the battery charging input, dock_dc, is provided to monitor for the presence of a battery charging docking station, or ac wall adaptor. monitoring is accomplish ed by a comparator-based approach, in which a programmable voltage reference is compared against the monitored signal. each channel possesses a dedicated reference voltage generated by a programmable level shifting digital to analog converter. the SMB118 and smb218 contain three user programmable voltage-monitoring levels, each of which triggers a corresponding status pin when exceeded. battery voltage, like all monitored voltages, is compared against a user programmable voltage set internally by a digital to analog converter. the dock_dc pin is a power input pin that can be used to power the SMB118 and smb218, and also to indicate the presence, and level, of a supplemental input like that supplied by a docking station or ac wall adaptor. it has a user programmable threshold from 3.4-4.8 volts at 200mv increments. when the user programmable voltage level for this pin is exceeded, continuously, for a de-bounced period in excess of 100 ms the dc_in pin will be asserted. when asserted, the power_fail pin is latched and will not be released as long as the voltage on the battery is below the power_fail level. once the voltage on the battery has risen above the power_fail level one of three conditions may clear the latch and allow the power_fail pin to be released: if the nbatt_fault output pin is asserted and released, if the dc_in output pin is asserted, and finally if an i 2 c power fail clear command is issued. once one of these conditions has been met, the power_fail pin will be released after a power-fail timeout period (t pfto ) of 3.0-4.5ms. the power_fail level is user programmable from 2.55-3.6v in 150 mv increments. when the voltage at the vbatt pin falls below the second user programmable level (available for SMB118 only), the active low nbatt_fault pin will be asserted. this pin is not latched and is used to indicate the impending loss of power to the SMB118. after the nbatt_fault pin has been asserted, a battery fault timeout period (t bfto ) of 3.0-4.5ms must pass in which the battery voltage exceeds the nbatt_fault threshold before it will be released. the nbatt_fault threshold is user programm able from 2.55-3.6.0v at 150 mv increments. normally dock dc, power fail, and battery fault thresholds are set in descending order respectively. upon assertion of either the nbatt_fault or power_fail pin the SMB118 and smb218 can be programmed to respond in one of three ways, they may perform: a power-off operation, a force-shutdown operation, or take no action. when programmed to perform a power-off or force-shutdown operation the devices can optionally be programmed to latch the outputs off until the power on pin is toggled or an i 2 c power-on command is issued. ldo standby voltage the ldo has a programmable output voltage from 1.5v to 3.75v. it is capable of supplying up to 75ma (typical) and has uv and ov monitoring levels with corresponding fault responses. the channel 2 ldo can be sequenced on in any of the six sequence positions, and can be enabled and disabled at any time. output voltage the pwm output voltages are set by a resistive voltage divider from the output to the compa or fb node; see figure 4. for the buck channel s (ch[6:4]), the voltage divider is internal to the part and programmable. the resistive divider may be set by adjusting a 100k ? resistor string with 8 taps from r1 = 20-90k ? . for the boost output (ch[1]), the re sistive divider is external and any appropriate value of r1 an r2 can be chosen. the reference voltage that sets the output is user programmable, and may be set anywhere from 0-1.000 volt at 4mv increments. battery charger the SMB118 and smb218 are equipped with a fully programmable lithium ion battery charger. the programmable feature set includes fast and pre-charge option, each with a programmable charge current level, a charge termination timeout period, an over and under temperature limit, multiple allowable recharge events, fault logging that can be accessed via the i 2 c interface and a general purpose output used to indicate the current status of the battery. please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 22 applications information (continued) battery charging is initiated by the detection a dc voltage on the dock_dc input. when the voltage on dock_dc exceeds the programmed minimum threshold voltage, the dc_in pin will be asserted indicating the successful connection of a charging input. once the charging voltage exceeds the dock_dc threshold voltage, the SMB118 will be powered from the dock_dc pin. once the voltage on dock_dc is above the programmed setting, battery charging will automatically commence. however, a programmable option allows the user to prevent battery charging until an i 2 c command has been issued. the shdn pin is bypassed once voltage is sensed on the dock_dc pin. trickle charge once all pre-qualification conditions are met, the devices check the bsense voltage to decide if trickle charging is required. if the battery voltage is below approximately 2.0v, a charging current of 2ma (typical) is applied on the battery cell. this allows the SMB118 and smb218 to reset the protection circuit in the battery pack and bring the battery voltage to a higher level without compromising safety. pre-charge mode once the battery voltage crosses the 2.0v level, the SMB118 and smb218 will begin to pre-charge the battery to safely charge the deeply discharged cells. the device stays in this mode until the voltage on bsense input is above t he programmed pre-charge threshold voltage. the pre-charge threshold voltage is programmable from 2.5v to 3.2v in 100mv increments. the pre-charge current is programmable from 25 to 250ma, in 15ma increments. fast-charge mode after the pre-charge threshold voltage has been exceeded, the battery charging current will be increased from the pre-charge current to the fast- charge current. the fast-charge current is programmable from 100ma to 1a, in 60ma increments. the battery will be charged wi th the fast- charge current until the battery voltage exceeds the final float voltage. taper charge mode once the final float voltage has been reached, the battery charger will enter a constant voltage taper charging mode, in which the battery voltage is held at the final float voltage. the taper charging mode will continue until the charge current drops below the termination current threshold. the termination current threshold is programmable at 100ma, 115ma, 130ma and 145ma, assuming a 100m ? sense resistor. a programmable option allows the taper charge mode to be bypassed and the battery charging to be completed once the final float voltage has been reached. current scaling all charging currents are determined by measuring the voltage across the battery cu rrent sense resistor. all programmable currents are based on the use of a 100m ? sense resistor. currents can be increased or decreased by scaling the current sense resistor. for example, a 50m ? sense resistor will scale the charging current by a factor of two, while using a 200m ? resistor will scale the charging current by one half. temperature monitoring to inhibit charging when the battery temperature is outside normal operating range a temperature sensing input is provided. the battery temperature is measured by sensing the voltage between the tsense pin and ground. the voltage is created by injecting a current into the parallel combination of negative temperature coefficient (ntc) thermistor and a resistor. as the temperature changes, the resistance of the thermistor changes creating a voltage proportional to temperature. this voltage is then compared to two predetermined voltages representing the maximum and minimum temperature settings of the battery. the purpose of the resistor in parallel to the nt c thermistor is to linearize the resistance of the thermi stor. table 1, shows the 1% resistor that should be placed in parallel with the corresponding thermistor. the temperature coefficient or beta ( ) of the thermistor must be as close to 4400 as possible to achieve the maximum temperature accuracy. ntc thermistor resistance 10k 24.9k 25k 61.9k 100k 249k table 1: ntc values and associated parallel resistances. if the temperature limits are exceeded, battery charging will be suspend until the battery voltage has fallen within the safe operating range.. the over temperature limit is programmable from 30 c to 65 c in 5 c please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 23 applications information (continued) increments. the under temperature limit is programmable from ? 20 c to 15 c in 5 c increments. charge termination timers there are two timers on the SMB118 and smb218 used to disable battery charging. the first timer is used to limit the allowable pre-charge duration. this timer begins when trickle charging is completed and ends when fast charging begins. it can be programmed to one of three settings: 44 minutes, 1 hour 27 minutes, and 2 hours 55 minutes. the second timer limits the fast-charge and taper charge duration. this time r begins when pre-charge mode is completed and ends when taper charging has been terminated. it is programmable in three settings, 5 hours 48 minutes, 11 hours 36 minutes, and 23 hours. each timer can be independently disabled. programmable switching frequency the SMB118 and smb218 have a 1mhz switching frequency. if a different frequency is desirable, please contact the summit factory. SMB118/218 battery charger vdd bsense bfetdrv bcsh bchl dock_dc tsense 10k ? ntc usb ac adaptor r cs figure 7 ? battery charging circuit please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 24 2v 3v 4v 200ma 1000ma 400ma 600ma 800ma t(precharge) 2500 sec t(charge) 20000 sec c h a r g i n g v o l t a g e c h a r gi n g c u r r e nt f l o a t v o l t a g e p r e c h a r g e t o f a s t c h a r g e t r a n s i t i o n ( d e e p d i s c h a r g e t h r e s h o l d ) f a s t c h a r g e t o t a p e r c h a r g e t r a n s i t i o n c h a r g e t e r m i n a t i o n figure 8 ? battery charging algorithm. battery charging algorithm please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 25 charger standby mode (timerrs preserved) vdd > vbatt + 200mv ? (always monitored) no por or shdn release yes vbattt>t(lo)? (always monitored) yes no reset t(charge) timer figure 9 ? battery charging flowchart. battery charging flowchart please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 26 buck converters the SMB118 and smb218 have three synchronous buck converters with integrated p-channel mosfets and a driver for an external nfet, see figure 10. each channel has an output voltage range from the input supply to approximately 0.5v. buck channel asynchronous operation the buck converters use either a constant frequency or variable frequency current mode control technique. during the fixed frequency pwm mode of operation, the converter switches at a fixed frequency and modulates the duty cycle to attain the correct output voltage. this can lead to ?charge shuttling? under light load conditions were the charge delivered to the output capacitor during the on time of the pfet is discharged to ground during the on time of the nfet. this mode of operation is desirable in sit uations requiring low voltage ripple, the ability to sink cu rrent, or a known switching frequency for all loads. during the pfm mode of operation the converter operates asynchronously where the fet is held off and the body diode of the fet is used as a ?catch? diode; preventing the voltage on the switch node from falling below ground by more than a diode drop. it is desirable to operate asynchronously under light load so that charge shuttling does not occur. the asynchronous operation allows the converter to only switch when the voltage falls below the error amplifier reference voltage. while it is advantageous to operate asynchronously for light load currents, it is less efficient for moderate loads where the power loss across the forward voltage drop of the diode leads to decreased efficiency. to increase the efficiency for these moderate load conditions an external schottky diode can be placed in parallel with the body diode of the fet. to maximize the converter efficiency for both light and heavy loads the buck converters automatically switch from pfm to pwm mode for higher loads. the pwm to pfm crossover is accomplished by observing the voltage on the comp pin, the voltage on the comp pin is directly proportional to the load current. when the voltage on the comp pin falls below a programmable reference, the converter operates in pfm. the drivers will stay in this state until t he voltage on the comp pins rise above the programmable pfm to pwm crossover voltage. each channel has an over current protection mechanism. when a channel reaches its current limit, the output voltage will be reduced as the load rises. this is accomplished by clamping the comp node to one of four programmable se ttings. the over-current level can be programmed to four different levels by clamping the error amplifier's output voltage to a programmable voltage. all current limits and pfm to pwm crossover currents are calculated by the gui interface. the output of all buck converters is determined by the portion of the switching period for which the inductor voltage is at the converter supply voltage, this percentage is referred to as the duty cycle. for a buck channel operating synchr onously duty cycle and the output voltage are related by equation 1 below: equation 1: vin d vo * = each buck converter can operate up to 100% duty cycle allowing the output to equal the input. the minimum voltage is determined by the minimum duty cycle listed in the electrical specifications section. for a buck converter operating in pfm mode the duty cycle is essentially 0% implying that the output can go to ground. each converter has a separate vin input used to power the converter. this supply attaches to the source of the integrated pfet. it is important to connect an input (or bulk) as close to the vin pin as possible. for information on the type of capacitor to use, refer to the component selection section. boost controller the SMB118 and smb218 have one asynchronous current mode boost converter with over-current protection and either a pwm or pfm mode of operation. as a current mode boost controller a sense resistor must be added, externally, in series with the source of the n-channel mosfet, see figure 11. the over- applications information (continued) sw vin drvl pwm comp vo comp fb figure 10 ? buck channel with internal pfet. please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 27 current circuitry is identical to that descried for the buck converter, the current limit is displayed in the gui. the pwm to pfm crossover current is identical to the circuitry used for the buck converter, we monitor the voltage on the comp node and when the voltage is below a programmable reference the nfet is held off. the boost converter has a fixed pwm option, when enabled the boost channel will switch every cycle keeping the ripple voltage low. care must be taken in selecting the pwm option on the boost channel, as this converter does not have the ab ility to shuttle charge. as a result, the load must be sufficient to deplete the deposited charge every cycle or else the output voltage will rise above the output set point. all boost controller drivers are powered from the vbatt supply pin. therefore, without voltage on the vbatt input the boost converters will not function. the output of all boost controllers are determined by the portion of the switching period for which the inductor voltage is at ground, this percentage is referred to as the duty cycle. for a boost controller where the inductor current does not go to 0a during the cycle (ccm) the relation between the duty cycle and the output voltage is determined by equation 2 below: equation 2: vin d vo * 1 1 ? ? ? ? ? ? ? = the maximum duty cycle the boost converter can achieve is determined by the max duty cycle specified in the electrical specification section of the datasheet. figure 11: boost channel boost or buck controller the SMB118 and smb218 have one voltage mode output that can be configured as either a boost or a buck controller; see figures 12 and 13. pchseq vin drvl pwm comp compa boost vout vin sequencing compb x drvh figure 12 ?buck or boost channel configured as boost. pchseq vin drvl pwm comp compa buck vout vin sequencing compb drvh figure 13 ? buck or boost channel configured as buck. a type three-compensation network is used for this voltage mode controller to provide optimal transient response. both configurations can operate in pwm or pfm mode. in addition, when configured a buck the output is allowed to reach a 100% duty cycle and operate in a low dropout mode. this is not to be confused with a buck-boost converter that can act as a buck if the output is below the input or a boost if the output is below the input. applications information (continued) pchseq vin drvl pwm compensation comp fb boost vout vddp sequencing csh csl rcs please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 28 component selection buck outputs: inductor: the starting point design of any and dc/dc converter is the selection of the appropriate inductor for the application. the optimal inductor value will set the inductor current at 30% of the maximum expected load current. the inductors current for buck and boost converters are as follows: buck: equation 3: f i vin vo v vo l max in * * 3 . 0 * ) ( ? = boost: equation 4: f i v v v v l max o in o in * * 3 . 0 * ) ( ? = where vo is the output voltage, vin is the input voltage, f is the frequency, and i max is the max load current. for example: for a 1.2v output and a 3.6v input with a 500ma max load, and a 1mhz switching frequency the optimal inductor value is: uh e l 3 . 5 6 1 * 5 . 0 * 3 . 0 * 6 . 3 ) 2 . 1 6 . 3 ( 2 . 1 = ? = choosing the nearest standard inductor value we select a 5.6uh inductor. it is import ant that the inductor has a saturation current level greater than 1.2 times the max load current. other parameters of interest when selecting an inductor are the dcr (dc winding resist ance). this has a direct impact on the efficiency of the converter. in general, the smaller the size of the inductor is the larger the resistance. as the dcr goes up the power loss increases according to the i 2 r relation. as a result choosing a correct inductor is often a trade off between size and efficiency. input capacitor each converter should have a high value low impedance input (or bulk) capacitor to act as a current reservoir for the converter st age. this capacitor should be either a x5r or x7r mlcc (multi-layer-ceramic capacitor). the value of this capacitor is normally chosen to reflect the ratio of the input and output voltage with respect to the output capacitor. typical values range from 2.2uf to 10uf. for buck converters, the input capacitor supplies square wave current to the inductor and thus it is critical to place this capacitor as close to the pfet as possible in order to minimize trace inductance that would otherwise limit the rate of change of the current. while the placement of this inductor for boost channels is not as critical as with the buck channels, each boost must still have its own rese rvoir capacitor. output capacitor each converter should have a high value low impedance output capacitor to act as a current reservoir for current transients and to. this capacitor should be either a x5r or x7r mlcc. for a buck converter, the value of this capacitance is determined by the maximum expected transient current. since the converter has a finite response time, during a load transient the current is provided by the output capacitor. since the voltage across the capacitor drops proportionally to the capacitance, a higher output capacitor reduces the voltage drop until the feedback loop can react to increase the voltage to equilibrium. for the boost converters, the output is disconnected from the inductor while the diode is reverse biased. this means that the entire load current is being taken from the output capacitance for this portion of the duty cycle. for this reason it is necessary to choose the output capacitor such that the cycle-to-cycle voltage droop is minimized to be within system limits. the voltage drop can be calculated according to: equation 5 : where i is the load or transient current, t is the time the output capacitor is supporting the output and c is the output capacitance. typical values range from 10uf to 44uf. other important capacitor parameters include the equivalent series resistance (e.s.r) of the capacitor. the esr in conjunction with the ripple current determines the ripple voltage on the output, for typical values of mlcc the esr ranges from 2-10m ? . in addition, carful attention must be paid to the voltage rating of the capacitor the voltage rating of a capacitor must never be exceeded. in addition, the dc bias voltage rating can reduce the measured capacitance by as much as 50% when the voltage is at half of the max rating, make sure to look at the dc bias de-rating curves when selecting a capacitor. applications information (continued) c t i v * = please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 29 mosfets when selecting the appropriate fet to use attention must be paid to the gate to source rating, input capacitance, and maximum power dissipation. most fets are specified by an on resistance (rds on ) for a given gate to source voltage (v gs ). it is essential to ensure that the fets used will always have a v gs voltage grater then the minimum value shown on the datasheet. it is worth noting that the specified v gs voltage must not be confused wi th the threshold voltage of the fet. the input capacitance must be chosen such that the rise and fall times specified in the datasheet do not exceed ~5% of the switching period. to ensure the maximum load current will not exceed the power rating of the fet, the power dissipation of each fet must be determined. it is important to look at each fet individually and then add the power dissipation of complementary fets after the power dissipation over one cycle has been determined. the power dissipation can be approximated as follows: equation 6: on l dson t i r p * * ~ 2 where t on is the on time of the primary switch. t on can be calculated as follows: equations 7, 8, 9: t v v v boost t v v pfet buck t v v nfet buck o in o in o in o * ) ( : * : * ) 1 ( : ? ? ? ? compensation: summit provides a design tool to called summit power designer? that will automatically calculate the compensation values for a design or allow the system to be customized for a particular application. the power designer software can be found at http://www.summitmicro.com/prod_select/xls/summitpo werdesigner_install.zip . applications information (continued) please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 30 development hardware & software the end user can obtain the summit smx3200 parallel port programming system or the i 2 c2usb (smx3201) usb programming system for device prototype development. the smx3200(1) system consist of a programming dongle, cable and windows tm gui software. it can be ordered on the website or from a local representative. the latest revisions of all software and an application brief describing the smx3200 and smx3201 are available from the website ( http://www.summitmicro.com ). the smx3200 programming dongle/cable interfaces directly between a pc?s parallel port and the target application; while the smx3201 interfaces directly to the pc?s usb port and the target application. the device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the SMB118 and smb218 via the programming dongle and cable. an example of the connection interface is shown in figure 14. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this will ensure proper devic e operation in the end application. pin 9, 3.3v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200/smx301 interface cable connector. 9 7 5 3 1 10 8 6 4 2 SMB118 smb218 sda scl dock_dc gnd 0.1 f d1 1n4148 figure 14 ? smx3200-3.3 programmer i 2 c serial bus connections to program the SMB118 or smb218. please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 31 i 2 c programming information serial interface access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standar d 2-wire serial interface (i 2 c). sda is a bi-directional data line and scl is a clock input. data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with the msb. during data transfers, sda must remain stable while scl is high. data is transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. the scl high period (t high ) is used for generating star t and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while scl is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 7-bit device type identifier (slave address). the remaining bit indicates either a read or a write operation. refer to table 1 for a description of the address bytes used by the SMB118 and smb218. the device type identifier for the memory array, the configuration registers an d the command and status registers are accessible with the same slave address. the slave address can be can be programmed to any seven bit number 0000000 bin through 1111111 bin . write writing to the memory or a configuration register is illustrated in figu res 15, 16, 18, and 19. a start condition followed by the slave address byte is provided by the host; the SMB118 responds with an acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMB118 and smb218 respond with an acknowledge; the host then clocks in one byte of data. for memory and c onfiguration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the non-volatile configuration registers and memory registers as well as the volatile command and status registers must be set before data can be read from the SMB118 and smb218. this is accomplished by issuing a dummy write command, which is a write command that is not followed by a stop condition. a dummy write command sets the address from which data is read. after the dummy write command is issued, a start command followed by the address byte is sent from the host. the host then waits for an acknowledge and then begins clocking data out of the slave device. the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clocked out of consecutive addresses with the host providing an acknowledge after each byte. after the data is read from the desired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to figures 17 and 20 for an illustration of the read sequence. configuration registers the configuration registers are grouped with the general-purpose memory. writing and reading the configuration registers is shown in figures 15, 16 and 17. general-purpose memory the 96-byte general-purpose memory block is segmented into two continuous independently lockable blocks. the first 48-byte memory block begins at register address pointer a0 hex and the second memory block begins at the r egister address pointer c0 hex ; see table 1. each memory block can be locked individually by writing to a dedicated register in the configuration memory spac e. memory writes and reads are shown in figures 18, 19 and 20. please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 32 i 2 c programming information graphical user interface (gui) device configuration ut ilizing the windows based SMB118 graphical user interface (gui) is highly recommended. the software is available from the summit website ( www.summitmicro.com ). using the gui in conjunction with this datasheet, simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3201) is available from summit to communicate with the SMB118 and smb218. the dongle connects directly to the usb port of a pc and programs the device through a cable using the i 2 c bus protocol. see figure 14 and the smx3201 data sheet. slave address register type configuration registers are located in 00 hex thru 9f hex general-purpose memory block 0 is located in a0 hex thru bf hex any general-purpose memory block 1 is located in c0 hex thru ff hex table 2 - address bytes used by the SMB118 and smb218. please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 33 i 2 c programming information (continued) s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 15 ? configuration register byte write s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 16 ? configuration register page write please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 34 i 2 c programming information (continued) s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k bus address a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 17 - configuration register read s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 18? general purpose memory byte write bus address s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 19 - general purpose memory page write please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 35 i 2 c programming information (continued) s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) bus address bus address a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 20 - general purpose memory read please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 36 48 pad qfn ? 7x7 package please note: the SMB118 has entered end-of-life.
SMB118/218 summit microelectronics, inc 2107 3.0 10/15/2008 37 summit SMB118n ayyww pin 1 annn summit part number date code (yyww) part number suffix (contains customer specific ordering requirements) lot tracking code (summit use) drawing not to scale xx status tracking code (01, 02, 03...) (summit use) product tracking code (summit use) l 100% sn, rohs compliant, green SMB118 n package n = 48-pad qfn summit part number SMB118 or smb218 specific requirements are contained in the suffix nnn part number suffix l l = 100% sn, rohs compliant c c = commercial temperature range environmental attribute blank = industrial notice note 1 - this is a final data sheet that describes a summit product currently in production. summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsib ility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect repres entative operating parameters, and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc . shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affe ct their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receive s written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all su ch risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. revision 3.0 ? this document supersedes all previous versions . please check the summit microelectronics inc. web site at http://www.summitmicro.com for data sheet updates. ? copyright 2008 summit microelectronics, inc. programmable power for a green world? i 2 c is a trademark of philips corporation ordering information part marking please note: the SMB118 has entered end-of-life.

▲Up To Search▲

Price & Availability of SMB118

	To Download SMB118 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .